1. Field of the Invention
The present invention relates generally to electrical circuits and devices. More particularly, the present invention relates to semiconductor packages, and circuit boards and methods for making semiconductor packages.
2. Related Art
Certain types of conventional semiconductor packages, such as ball grid array (BGA) packages, include an internal substrate. The substrate includes a core insulative sheet. Metal traces and a metal die pad are provided on a top surface of the substrate. Metal traces also are provided on an opposite bottom surface of the substrate. Metal-lined vias through the substrate electrically connect the metal traces on the top and bottom surfaces of the substrate. A semiconductor die is attached to the die pad on the top surface of the substrate. Bond wires electrically connect bond pads of the die to metal traces on the top surface of the substrate. A hardened encapsulant covers the die and bond wires, and the entire top surface of the substrate. Solder balls are fused to the metal traces on the bottom surface of the substrate. The solder balls, therefore, are electrically connected to the die through the metal traces, vias, and bond wires.
One drawback of this conventional package is that physical forces applied to the package may cause the solder balls to shear off the metal traces of the substrate. In addition, the packages cannot be stacked one on top of another due to the encapsulant. It also is difficult to test the package once the package is soldered to a motherboard, since the reflowed solder balls are not easily accessible from the periphery of the package, and the top of the package is covered with encapsulant.
Another drawback lies in the complexity of the process of making the substrate of the package. As mentioned above, metal traces are present on both the top and bottom surfaces of the substrate. To form these traces, metal substrates are laminated to the top and bottom surfaces of the core insulative sheet. Next, holes are drilled through the insulative sheet and the metal layers. Subsequently, the holes are plated with metal to form the vias, and both of the metal substrates are patterned by photolithography and etching to form the metal traces. Each of these steps costs time and money, and thus a simplification of the process would be advantageous.
In accordance with embodiments of the present invention, improved semiconductor packages and methods and circuit boards for making the semiconductor packages are provided.
In accordance with an embodiment of the present invention, a method of making an internal printed circuit board for a semiconductor package includes: providing an insulative sheet having a first surface and an opposite second surface; forming a plurality of first apertures and a second aperture through the sheet between the first surface and the second surface, wherein each first aperture is adapted to receive a solder ball and the second aperture is adapted to receive a semiconductor die; and subsequently forming a layer of conductive circuit traces on the first surface of the sheet. First portions of the conductive circuit traces overlie the first apertures, and ends of the circuit traces are proximate to the second aperture. The circuit traces may horizontally overhang the second aperture, or may be located outside the perimeter of the second aperture. No circuit traces are provided on the bottom surface of the printed circuit board. In an optional step, third apertures may also be formed through the first portions of the circuit traces, i.e., through the portions of the circuit traces overlying the first apertures.
In accordance with another embodiment of the present invention, a printed circuit board for making a semiconductor package includes: an insulative sheet having a first surface, an opposite second surface, a plurality of first apertures through the sheet, and a second aperture through the sheet, wherein the first apertures are each adapted to receive a solder ball and the second aperture is adapted to receive a semiconductor die; and a layer of conductive circuit traces on the first surface of the sheet, wherein respective first portions of the conductive circuit traces overlie respective first apertures, and ends of the conductive circuit traces extend over the second aperture. No circuit traces are provided on the bottom surface of the sheet in this embodiment.
In accordance with another embodiment of the present invention, a method of fabricating a semiconductor package includes: providing a printed circuit board as described above; placing a semiconductor die in the second aperture on the overhanging ends of the circuit traces; forming an electrical connection between the bond pads of semiconductor die and the overhanging ends of the circuit traces; placing a solder ball in each of the respective first apertures; and fusing the solder ball to the first portion of the circuit trace overlying the respective first aperture, thereby electrically connecting each solder ball to the die through a circuit trace. Optionally, the second aperture, the die, and an inner sub-portion of the printed circuit board around the second aperture are encapsulated.
In accordance with another embodiment of the present invention, a semiconductor package includes: a printed circuit board as described above; a plurality of solder balls, wherein each solder ball is in one of the respective first apertures and is fused to the overlying first portion of one of the circuit traces; and a semiconductor die in the second aperture. The die is mounted on the overhanging ends of the circuit traces and is electrically connected thereto. Optionally, the second aperture and the die may be encapsulated. The first apertures and the solder balls are outside a perimeter of the encapsulant.
The package design of the present invention prevents shearing of solder balls from the package by inserting the solder balls through an aperture in the substrate, thereby physically shielding the solder ball.
In other circuit board and package embodiments, third apertures are provided through the first portion of each of the circuit trace, i.e., through the portion of the respective circuit trace that overlies one of the first apertures. A portion of the solder of the solder ball subsequently provided in the first aperture fills the third aperture, so as to be exposed at the upper first surface of the circuit board. After the package is mounted on a motherboard, the exposed solder may be touched from above the circuit board of the package with a test probe in order to electrically test the electrical connection between the motherboard and the respective reflowed solder balls of the package. Of course, there is no encapsulant over the top surface of the circuit board opposite the solder balls in this embodiment, else the test probe could not make contact with the exposed portions of the solder balls.
Packages with such third apertures can easily be stacked in accordance with another embodiment of the present invention. An exemplary stack of semiconductor packages includes: at least first and second semiconductor packages, as described above, wherein the second package is mounted on top of the first package so that each solder ball of the second package is fused to a solder ball of the second package through a third aperture.
In a further embodiment, where the semiconductor die of each of the stacked packages is an optical device, the packages may be stacked so that the dies may be in optical communication with each other. In such an embodiment, a first semiconductor package is mounted on a motherboard so that the optical circuitry of the die faces away from the motherboard. A second semiconductor package is stacked on the first package so that the optical circuitry of the die of the second package faces the optical circuitry of the die of the first package and the motherboard. One or both of the packages may have an optically clear structure, such as a lid, lens, or optically clear encapsulant, that is provided over the optical circuitry of the die so as to transmit light to the optical circuitry.
These and other aspects of the present invention may be better understood by a consideration of the following detailed description and the appended drawings.